1. Technical Field
The invention relates to display devices. More specifically, the invention relates to calibration of analog to digital converters used in digital displays.
2. Background
FIG. 1 illustrates a broad schematic of an arrangement to generate images and to display the images in digital form. In particular, a host 102 (for example, a personal computer) generates an image in digital format. Digital to analog converter (DAC) circuitry 104 associated with the host 102 converts the digital image data generated by the host 102 into analog image data (typically, in RGB format) to be sent out over a connection 106 to digital display circuitry 108. Analog to digital converter (ADC) circuitry 110 associated with the digital display circuitry 108 converts the analog image data back into digital image data, which is then provided to a display 112 such as a liquid crystal (LCD). The operation of the digital display circuitry 108 is typically under the control of a processor (not shown) that is either “on-board” (or otherwise relatively tightly coupled to the circuitry of the digital display circuitry 108) or “off board” (or otherwise less tightly coupled to the circuitry of the digital display circuitry 108).
With particular respect to the ADC circuitry 110, variation in silicon process may result in internal offset voltages of the ADC circuitry 110 varying with temperature. As a result, when temperature varies, the RGB output data through the ADC circuitry 110 may show data drift.
The internal offset voltages depend on factors such as threshold voltage mismatch, overdrive voltage and transistor mismatches. The internal offset voltages are cancelled out depending on the values of OFFSET1 and OFFSET2 registers for each of the RGB colors, associated with the ADC circuitry 110. The OFFSET1 and OFFSET2 registers both have the same general effect, but the OFFSET1 register provides a relatively gross adjustment, while the OFFSET2 register provides a relatively finer adjustment. In one example, each one bit adjustment of the OFFSET1 register provides 1.7 bits of least significant bit (LSB) adjustment to the ADC circuitry 110 for a color channel, while each one bit adjustment of the OFFSET2 register provides 0.8 bits of LSB adjustment to the ADC circuitry 110 for the color channel. By appropriately setting the values in the OFFSET1 and OFFSET2 registers for each channel, the result is that the colors (RGB) will be balanced as a whole.
However, the terms in the equation for determining the offset values for the OFFSET1 and OFFSET2 registers have different temperature coefficients. It is thus difficult to predetermine how to vary these values with temperature change to achieve a perfect cancellation of these different temperature variations. Also, the temperature dependence varies with process, making it even more difficult to predetermine how to correlate the offset values to temperature.
Conventionally, offset values and gain values are initialized at the power up of the digital display circuitry 108 (including the ADC circuitry 110) and stored in a non-volatile RAM (NVRAM). Thus, color balance is achieved, at least initially. However, the output data from one or more channels of the ADC circuitry 110 may shift based on changes in operating conditions, such as changes in operating temperature.
It is thus desirable to respond to such changes in operating conditions and, in particular, to respond in a way that is not nominally visible to a typical viewer of images on the display 112.